Ultra-low voltage ultra-low power NMOS bulk-biased mixer
Latch behavior in partially-depleted SOI (PDSOI) NMOS/CMOS
Study on Channel Strain in Strained-Si NMOS Transistor by Simulation
Ultra-low voltage ultra-low power NMOS bulk-biased mixer
Latch behavior in partially-depleted SOI (PDSOI) NMOS/CMOS
Study on Channel Strain in Strained-Si NMOS Transistor by Simulation